Semiconductor integrated circuits can be formed from active devices, such as diodes or transistors, and from passive devices such as capacitors, resistors, and inductors, in any combination. Typical integrated circuits use a resistor pattern having high resistance. Conventionally, the resistor pattern of a semiconductor device is formed of doped polysilicon having a relatively high sheet resistivity (Rs). The polysilicon is used in various parts of fabricating the semiconductor integrated circuit. A gate electrode (i.e., part of an important active device) of the transistor typically includes a polysilicon layer. Capacitor electrodes (i.e., a storage electrode and a plate electrode) are also formed of polysilicon. However, since the transistor requires a low gate resistance for low power-dissipation and a high speed-operation, the gate electrode of the transistor is typically formed of a polycide layer comprising a stacked polysilicon layer and a silicide layer.
Among semiconductor memory devices, a FLASH memory device typically includes a floating gate formed of a single layer of polysilicon and a control gate electrode formed of a polycide layer.
As illustrated in FIG. 1, a device isolation layer 12 is disposed in a substrate 10 to define an active region 14. Source and drain regions 30s and 30d are disposed in the active region 14. A gate stack 16 including a floating gate 20a, a gate interlayer dielectric layer 24, and control gate electrodes 22, which are sequentially stacked, is disposed on a substrate between the source and drain regions 30s and 30d. In addition, a resistor pattern 18 is disposed on the device isolation layer 12 and resistor electrodes 28 are connected to both edges of the resistor pattern 18. The resistor electrodes 28 are long enough to extend through an interlayer dielectric layer 26, which covers the entire surface of the substrate.
As further illustrated in FIG. 1, the cell transistor of the FLASH memory device includes the floating gate 20a, which is formed of polysilicon. This enables a resist pattern to be formed using the polysilicon layer 20b that is also used for forming the floating gate 20a. 
FIG. 2 is a cross-sectional view of a conventional DRAM memory device.
Referring to FIG. 2, in the DRAM memory device, a device isolation layer 42, defining an active region 44, is disposed on a substrate 40, and source and drain regions 48s and 48d are disposed in the active region 44. A gate electrode 59 is disposed on a substrate between the source and drain regions 48s and 48d. A capacitor is connected to the source region 48s. The capacitor includes a lower electrode 60 connected to the source region 48s and an upper electrode 56a formed at each divided sector in a cell array region. To lower the gate resistance, the gate electrode 59 is formed of polycide that includes a polysilicon layer 50 and a silicide layer 54. Therefore, a resistor pattern may not be formed from the polysilicon layer 50 that forms the gate electrode 59. Thus, a resistor pattern 56b of the conventional DRAM memory device may be formed of a polysilicon layer that is used to form the lower electrode 60 or the upper electrode 56a. Resistor electrodes 58 are connected to both edges of the resistor pattern 56b. 
As explained above, the FLASH memory device and the DRAM memory device may include a step of forming a resistor pattern formed of a single polysilicon layer during each step of forming the floating gate and the capacitor, respectively. In a semiconductor device with a polycide gate electrode, a desired resistor pattern typically is formed by making a resistor pattern of a single polysilicon layer or by reducing the thickness or the width of the polysilicon layer. A method of fabricating a resistor pattern having high sheet resistance in a semiconductor device with a polycide gate is taught in U.S. Pat. No. 6,313,516 entitled “Method for Making High-Sheet-Resistance Polysilicon Resistors for Integrated Circuits”.
FIGS. 3-6 are cross-sectional views showing a method of fabricating a semiconductor device with a typical resistor pattern.
Referring to FIG. 3, a device isolation layer 62 is formed in a substrate 60 to define an active region 64, and source and drain regions 66s and 66d are formed in the active region 64. A gate electrode 78 is formed on an active region 64 between the source and drain regions 66s and 66d. An interconnection or a lower electrode 80 is formed on the device isolation layer 62.
A capacitor dielectric layer 76 is further formed on the entire surface of the resultant substrate. The gate electrode 78 and the capacitor lower electrode 80 are formed of polycide comprising polysilicon 70 and refractory metal silicide 72, which are sequentially stacked.
Referring to FIG. 4, a resistor pattern 88 is formed on the capacitor dielectric layer 76. The resistor pattern is formed by sequentially stacking a thin doped polysilicon layer 82 and a thick undoped polysilicon layer 84, thereby increasing sheet resistance.
Referring to FIGS. 5 and 6, an interlayer dielectric layer 86 is formed on the entire surface of the substrate with the resistor pattern 88. Next, electrodes 90 are formed to extend through the interlayer dielectric layer 86 and connect to both edges of the resistor pattern 88.
As explained above, since the sheet resistance of polycide is low, the resistor pattern cannot be formed during formation of the gate electrode. Therefore, separate steps for forming the gate pattern and forming the resistor pattern are required, and the gate electrode and the resistor pattern are formed on different layers, thus increasing a step difference of the device.
Embodiments of the invention address these and other limitations in the prior art.